1. Field of the Invention
This invention relates to semiconductor hybrid devices and methods of making same and primarily to such hybrid devices and methods of fabrication as applied to focal plane array circuits.
2. Brief Description of the Prior Art
Hybrid semiconductor devices have been fabricated in the past and involve the fabrication of a single semiconductor device using two different types of semiconductor materials, such as, for example, group II-VI or group III-V semiconductor compounds secured to silicon. Such hybrid devices have generally been utilized in the field of focal plane array devices, though other uses therefore are readily apparent and contemplated. Hybrid focal plane array circuits in the past have generally been fabricated in a one at a time mode whereas economics indicate that fabrication in a batch mode is preferable.
In the case of the focal plane array circuit, the device is generally a combination of a compound semiconductor material, such as, for example, mercury cadmium telluride (MCT) and silicon. Capacitors are fabricated in the compound semiconductor material which detect photons of infrared on the surface thereof with a via extending from the capacitors to conductive areas on the integrated circuit (IC) contained in the silicon. The capacitor is read out by connection thereof to an amplifier and/or other appropriate circuitry in the IC.
There have been problems associated with the contemplated batch mode fabrication of hybrid focal plane array circuits.
Hybridization, mating or encapsulation of semiconductor materials according to the prior art often causes stresses in the semiconductor material resulting in electrical performance degradation. It is therefore desirable to smooth the semiconductor device active surfaces to eliminate sites of high point stresses thereon whereby the upper surface of the IC appears planar to the compound semiconductor when viewed from the compound semiconductor surface mating with the IC. Likewise, it is desirable to eliminate stress due to mismatch in coefficients of thermal expansion of the materials in contact with each other. These stresses can result in dislocations in the material. Stresses introduced from topology at mated surfaces can result in high dark currents in focal plan arrays, for example, and therefore provide reduced well capacity, thus degrading electrical performance.
The compound semiconductor is generally secured to the silicon by means of an epoxy and results in a thermal mismatch between, for example, the MCT, the silicon and the organic mating compound (e.g. the epoxy). Since focal plane arrays generally operate at 77.degree. K., the temperature of liquid nitrogen, thermal mismatch becomes a serious problem. Because the various components have different temperature coefficients of expansion (TCE) and shrink at different rates during cooling, stresses are set up which degrade the electrical performance of the final hybrid device. It is therefore desirable that the stresses be distributed throughout the plane as uniformly as possible so that each pixel provides substantially the same output for a given light input.
To reduce dislocation defects in, for example, mercury cadmium telluride (MCT), the surface of the silicon integrated circuits (ICs) onto which the MCT will be mounted must be optically planar or better (i.e. &lt;7000 Angstroms peak to valley and preferably about 1000 Angstroms or less peak to valley). In general, however, the upper layers of ICs are composed of metal, typically aluminum, capped in silicon dioxide. Unlike planarizing between metal layers in standard IC processing, the objective in the fabrication of hybrid devices is to make the finished IC surface as planar as possible, this degree of planarity being much more severe than has previously been required or available.